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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad654 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: ? analog devices, inc., low cost monolithic voltage-to-frequency converter features low cost single or dual supply, 5 v to 36 v, 6 5 v to 6 18 v full-scale frequency up to 500 khz minimum number of external components needed versatile input amplifier positive or negative voltage modes negative current mode high input impedance, low drift low power: 2.0 ma quiescent current low offset: 1 mv product description the ad654 is a monolithic v/f converter consisting of an input amplifier, a precision oscillator system, and a high current output stage. a single rc network is all that is required to set up any full scale (fs) frequency up to 500 khz and any fs input voltage up to 30 v. linearity error is only 0.03% for a 250 khz fs, and operation is guaranteed over an 80 db dynamic range. the overall temperature coefficient (excluding the effects of external components) is typically 50 ppm/ c. the ad654 operates from a single supply of 5 v to 36 v and consumes only 2.0 ma quies- cent current. the low drift (4 m v/ c typ) input amplifier allows operation directly from small signals such as thermocouples or strain gauges while offering a high (250 m w ) input resistance. unlike most v/f converters, the ad654 provides a square-wave output, and can drive up to 12 ttl loads, optocouplers, long cables, or similar loads. product highlights 1. packaged in both an 8-lead mini-dip and an 8-lead soic package, the ad654 is a complete v/f converter requiring only an rc timing network to set the desired full-scale fre- quency and a selectable pull-up resistor for the open-collector output stage. any full scale input voltage range from 100 mv to 10 volts (or greater, depending on +v s ) can be accommo- dated by proper selection of the timing resistor. the full- scale frequency is then set by the timing capacitor from the simple relationship, f = v/10 rc. 2. a minimum number of low cost external components are necessary. a single rc network is all that is required to set up any full scale frequency up to 500 khz and any full-scale input voltage up to 30 v. 3. plastic packaging allows low cost implementation of the standard vfc applications: a/d conversion, isolated signal transmission, f/v conversion, phase-locked loops, and tuning switched-capacitor filters. 4. power supply requirements are minimal; only 2.0 ma of quiescent current is drawn from the single positive supply from 4.5 volts to 36 volts. in this mode, positive inputs can vary from 0 volts (ground) to (+v s C4) volts. negative inputs can easily be connected for below ground operation. 5. the versatile open-collector output stage can sink more than 10 ma with a saturation voltage less than 0.4 volts. the logic common terminal can be connected to any level between ground (or Cv s ) and 4 volts below +v s . this allows easy direct interface to any logic family with either positive or negative logic levels. functional block diagram 3 2 1 5 8 7 6 ad654 4 driver osc f out logic common r t +v in +v s c t c t Cv s 2013 781/461.3113 c
C2C rev. ad654Cspecifications (t a = +25 8 c and v s (total) = 5 v to 16.5 v, unless otherwise noted. all testing done @ v s = +5 v.) ad654jn/jr model min typ max units current-to-frequency converter frequency range 0 500 khz nonlinearity 1 f max = 250 khz 0.06 0.1 % f max = 500 khz 0.20 0.4 % full-scale calibration error c = 390 pf, i in = 1.000 ma C10 +10 % vs. supply (f max 250 khz) v s = +4.75 v to +5.25 v 0.20 0.40 %/v v s = +5.25 v to +16.5 v 0.05 0.10 %/v vs. temp (0 c to +70 c) 50 ppm/ c analog input amplifier (voltage-to-current converter) voltage input range single supply 0 (+v s C 4) v dual supply Cv s (+v s C 4) v input bias current (either input) 30 50 na input offset current 5 na input resistance (noninverting) 250 m w input offset voltage 0.5 1.0 mv vs. supply v s = +4.75 v to +5.25 v 0.1 0.25 mv/v v s = +5.25 v to +16.5 v 0.03 0.1 mv/v vs. temp (0 c to +70 c) 4 m v/ c output interface (open collector output) (symmetrical square wave) output sink current in logic 0 2 v out = 0.4 v max, +25 c 10 20 ma v out = 0.4 v max, 0 c to +70 c510 ma output leakage current in logic 1 10 100 na 0 c to +70 c 50 500 na logic common level range Cv s (+v s C 4) v rise/fall times (c t = 0.01 m f) i in = 1 ma 0.2 m s i in = 1 m a1 m s power supply voltage, rated performance 4.5 16.5 v voltage, operating range single supply 4.5 36 v dual supply 5 18 v quiescent current v s (total) = 5 v 1.5 2.5 ma v s (total) = 30 v 2.0 3.0 ma temperature range operating range C40 +85 c notes 1 at f max = 250 khz; r t = 1 k w , c t = 390 pf, i in = 0 maC1 ma. 1 at f max = 500 khz; r t = 1 k w , c t = 200 pf, i in = 0 maC1 ma. 2 the sink current is the amount of current that can flow into pin 1 of the ad654 while maintaining a maximum voltage of 0.4 v between pin 1 and logic common. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. specifications subject to change without notice. c
ad654 rev. c | page 3 absolute maximum ratings parameter rating total supply voltage +v s to ?v s 36 v maximum input voltage (pins 3, 4) to ?v s ?300 mv to +v s maximum output current instantaneous 50 ma sustained 25 ma logic common to ?v s ?500 mv to (+v s C4) storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad654 C4C rev. circuit operation the ad654s block diagram appears in figure 1. a versatile operational amplifier serves as the input stage; its purpose is to convert and scale the input voltage signal to a drive current in the npn follower. optimum performance is achieved when, at the full-scale input voltage, a 1 ma drive current is delivered to the current-to-frequency converter (an astable multivibrator). the drive current provides both the bias levels and the charging current to the externally connected timing capacitor. this adaptive bias scheme allows the oscillator to provide low nonlinearity over the entire current input range of 100 na to 2 ma. the square wave oscillator output goes to the output driver which provides a floating base drive to the npn power transistor. this floating drive allows the logic interface to be referenced to a level other than Cv s . osc/ driver ad654 optional r comp cr1 Cv s ( 0v to C15v ) r1 r2 v in +v s (+5v to Cv s +30) c t +v logic r pu f out f out = v in (10v) (r1 + r2) c t figure 1. standard v-f connection for positive input voltages v/f connection for positive input voltages in the connection scheme of figure 1, the input amplifier presents a very high (250 m w ) impedance to the input voltage, w hich is converted into the proper drive current by the scaling resistors at pin 3. resistors r1 and r2 are selected to provide a 1 ma full-scale current with enough trim range to accommodate the ad654s 10% fs error and the components tolerances. f ull- scale currents other than 1 ma can be chosen, but linearity will be reduced; 2 ma is the maximum allowable drive. the ad654s positive input voltage range spans from Cv s (ground in sink supply operation) to four volts below the positive supply. power sup- ply rejection degrades as the input exceeds (+v s C 3.75 v) and at (+v s C 3.5 v) the output frequency goes to zero. as indicated by the scaling relationship in figure 1, a 0.01 m f timing capacitor will give a 10 khz full-scale frequency, and 0.001 m f will give 100 khz with a 1 ma drive current. good v/f linearity requires the use of a capacitor with low dielectric absorption (da), w hile the most stable operation over tempera- ture calls for a component having a small tempco. polystyrene, polypropy lene, or teflon* capacitors are preferred for tempco and dielectric absorption; other types will degrade linearity. the capacitor should be wired very close to the ad654. in figure 1, schottky diode cr1 (mbd101) prevents logic common from dropping more than 500 mv below Cv s . this diode is not required if Cv s is equal to logic common. v/f connections for negative input voltage or current the ad654 can accommodate a wide range of negative input voltages with proper selection of the scaling resistor, as indicated in figure 2. this connection, unlike the buffered positive con- nection, is not high impedance because the signal source must supply the 1 ma fs drive current. however, large negative volt- ages beyond the supply can be handled easily by modifying the scaling resistors appropriately. if the input is a true current source, r1 and r2 are not used. again, diode cr1 prevents latch-up by insuring logic common does not drop more than 500 mv below Cv s . the clamp diode (mbd101) protects the ad654 input from below Cv s inputs. osc/ driver ad654 optional r comp cr1 Cv s (0v to C15v) r1 r2 +v s (+5v to Cv s +30) c t +v logic r pu f out f out = v in (10v) (r1 + r2) c t v in clamp diode figure 2. v-f connections for negative input voltages or current offset calibration in theory, two adjustments calibrate a v/f: scale and offset. in practice, most applications find the ad654s 1 mv max voltage offset sufficiently low to forgo offset calibration. however, the input amplifiers 30 na (typ) bias currents will generate an offset due to the difference in dc sound resistance between the input terminals. this offset can be substantial for large values of r t = r1 + r2 and will vary as the bias currents drift over temperature. therefore, to maintain the ad654s low offset, the application may require balancing the dc source resistances at the inputs (pins 3 and 4). for positive inputs, this is accomplished by adding a compensation resistor nominally equal to r t in series with the input as shown in figure 3a. this limits the offset to the product of the 30 na bias current and the mismatch between the source resistance r t and r comp . a second, smaller offset arises from the inputs 5 na offset current flowing through the source resistance r t or r comp . for negative input voltage and current connections, the compensa- tion resistor is added at pin 4 as shown in figure 3b in lieu of grounding the pin directly. for both positive and negative inputs, the use of r comp may lead to noise coupling at pin 4 and should therefore be bypassed for lowest noise operation. r1 r2 v in r comp ad654 (optional) c figure 3a. bias current compensationpositive inputs *teflon is a trademark of e.i. du pont de nemours & co. c
ad654 rev. C5C (optional) c r1 r2 v in r comp ad654 figure 3b. bias current compensationnegative inputs if the ad654s 1 mv offset voltage must be trimmed, the trim must be performed external to the device. figure 3c shows an optional connection for positive inputs in which r off1 and r off2 add a variable resistance in series with r t . a variable source of 0.6 v applied to r off1 then adjusts the offset 1 mv. similarly, a 0.6 v variable source is applied to r off in fig- ure 3d to trim offset for negative inputs. the 0.6 v bipolar source could simply be an ad589 reference connected as shown in figure 3e. v in 10kv ad654 5kv 8.25kv r off2 20v r off1 10kv 6 0.6v figure 3c. offset trim positive input (10 v fs) v in 10kv ad654 5kv 8.25kv r off 5.6mv 6 0.6v figure 3d. offset trim negative input (C10 v fs) +5v r3 10kv 6 0.6v r4 10kv r5 100kv + C ad589 r1 10kv r1 10kv r2 10kv C5v figure 3e. offset trim bias network full-scale calibration full-scale trim is the calibration of the circuit to produce the desired output frequency with a full-scale input applied. in most cases this is accomplished by adjusting the scaling resistor r t . precise calibration of the ad654 requires the use of an accurate voltage standard set to the desired fs value and an accurate frequency meter. a scope is handy for monitoring output wave- shape. verification of converter linearity requires the use of a switchable voltage source or dac having a linearity error below 0.005%, and the use of long measurement intervals to mini- mize count uncertainties. since each ad654 is factory tested for linea rity, it is unnecessary for the end-user to perform this tedious and time consuming test on a routine basis. sufficient fs calibration trim range must be provided to accom- modate the worst-case sum of all major scaling errors. this includes the ad654s 10% full-scale error, the tolerance of the fixed scaling resistor, and the tolerance of the timing capacitor. therefore, with a resistor tolerance of 1% and a capacitor tolerance of 5%, the fixed part of the scaling resistor should be a maximum of 84% of nominal, with the variable portion selected to allow 116% of the nominal. if the input is in the form of a negative current source, the scaling resistor is no longer required, eliminating the capability of trim- ming fs frequency in this fashion. since it is u sually not practical to smoothly vary the capacitance for trimming purposes, an alternative scheme such as the one shown in figure 4 is needed. designed for a fs of 1 ma, this circuit divides the input into two ad654 r off 100kv r4 392v r3 1kv 6 0.6v * *optional offset trim f = i s (20v) c t i r Cv 1ma fs i s r2 100v r1 100v figure 4. current source fs trim and flowing into pin 3; it constitutes the signal current i t to be converted. the second path, through another 100 w resistor r2, carr ies the same nominal current. two equal valued resistors offer the best overall stability, and should be either 1% discrete film units, or a pair from a common array. since the 1 ma fs input current is divided into two 500 m a legs (one to ground and one to pin 3), the total input signal current (i s ) is divided by a factor of two in this network. to achieve the same conversion scale factor, c t must be reduced by a factor of two. this results in a transfer unique to this hookup: f = i s (20 v ) c t for calibration purposes, resistors r3 and r4 are added to the network, allowing a 15% trim of scale factor with the values shown. by varying r4s value the trim range can be modified to accommodate wider tolerance components or perhaps the cali- bration tolerance on a current output transducer such as the ad592 temperature sensor. although the values of r1Cr4 shown are valid for 1 ma fs signals only, they can be scaled upward proportionately for lower fs currents. for instance, they should be increased by a factor of ten for a fs cu rrent of 100 m a. in addition to the offsets generated by the input amplifiers bias and offset currents, an offset voltage induced parasitic current arises from the current fork input network. these effects are minimized by using the bias current compensation resistor r off and offset trim scheme shown in figure 3e. although device warm-up drifts are small, it is good practice to allow the devices operating environment to stabilize before trim, c
ad654 C6C rev. and insure the supply, source and load are appropriate. if pr ovision is made to trim offset, begin by setting the input to 1/10,000 of full scale. adjust the offset pot until the output is 1/10,000 of full scale (for example, 25 hz for a fs of 250 khz). this is most easily accomplished using a frequency meter connected to the output. the fs input should then be applied and the gain pot should be adjusted until the desired fs frequency is indicated. input protection the ad654 was designed to be used with a minimum of additional hardware. however, the successful application of a precision ic involves a good understanding of possible pitfalls and the use of suitable precautions. thus +v in and r t pins should not be driven more than 300 mv below Cv s . likewise, logic common should not drop more than 500 mv below Cv s . this would cause inter- nal junctions to conduct, possibly damaging the ic. in addition to the diode shown in figures 1 and 2 protecting logic common, a second schottky diode (mbd101) can protect the ad654s inputs from below Cv s inputs as shown in figure 5. it is also desirable not to drive +v in and r t above +v s . in operation, the converter will exhibit a zero output for inputs above (+v s C 3.5 v). also, control currents above 2 ma will increase nonlinearity. the ad654s 80 db dynamic range guarantees operation from a control current of 1 ma (nominal fs) down to 100 na (equiva- lent to 1 mv to 10 v fs). below 100 na improper operation of the oscillator may result, causing a false indication of input amplitude. in m any cases this might be due to short-lived noise spikes which become added to input. for example, when scaled to accept an fs input of 1 v, the C80 db level is only 100 m v, so when the mean input is only 60 db below fs (1 mv), noise spikes of 0.9 mv are sufficient to cause momentary malfunction. this effect can be minimized by using a sim ple low-pass filter ahead of the converter or a guard ring around the r t pin. the filter can be assembled using the bias current comp ensation resistor discussed in the previous section. for an fs of 10 khz, a single-pole filter with a time constant of 100 ms will be suitable, but the optimum configuration will depend on the application and the type of signal processing. noise spikes are only likely to be a cause of error when the input current remains near its mini- mum value for long periods of time; above 100 na full integration of additive input noise occurs. like the inputs, the capacitor terminals are sensitive to interference from other signals. the timing capacitor should be located as close as possible to the ad654 to m inimize signal pickup in the leads. in some cases, guard rings or shielding may be required. ad654 mbd101 i in figure 5. input protection decoupling it is good engineering practice to use bypass capacitors on the supply-voltage pins and to insert small-valued resistors (10 to 100 w ) in the supply lines to provide a measure of decoupling between the various circuits in the system. ceramic capacitors of 0.1 m f to 1.0 m f should be applied between the supply- voltage pins and analog signal ground for proper bypassing on the ad654. a proper ground scheme appears in figure 6. 8 1 7 2 6 3 5 4 ad654 +5v gnd digital p.s. 10v 0.1mf c t r t r pu f out agnd v in figure 6. proper ground scheme output interfacing consideration the output stages design allows easy interfacing to all digital logic families. the output npn transistors emitter and collector are both uncommitted. the emitter can be tied to any voltage between Cv s and 4 volts below +v s , and the open collector can be pulled up to a voltage 36 volts above the emitter regardless of +v s . the high power output stage can sink over 10 ma at a maximum saturation voltage of 0.4 v. the stage limits the output current at 25 ma and can handle this limit indefinitely without damag- ing the device. nonlinearity specification the preferred method of specifying nonlinearity error is in terms of maximum deviation from the ideal relationship after calibrat- ing the converter at full scale. this error will vary with the full scale frequency and the mode of operation. the ad654 operates best at a 150 khz full-scale frequency with a negative voltage input; the linearity is typically within 0.05%. operating at higher fre- quencies or with positive inputs will degrade the linearity as indicated in the specifications table. typical linearity at various temperatures is shown in figure 7. full-scale frequency C khz 10 0.01 10 maximum nonlinearity C % 1 150 250 350 500 5 0.5 0.10 0.05 f amb = C408c f amb = 08c to +858c figure 7. typical nonlinearities at different full-scale frequencies c
ad654 rev. C7C two-wire temperature-to-frequency conversion figure 8 sh ows the ad654 in a two-wire temperature-to-frequency conversion scheme. the twisted pair transmission line serves the dual purpose of supplying power to the device and also carrying frequency data in the form of current modulation. the positive supply line is fed to the remote v/f through a 140 w resistor. this resistor is selected such that the quiescent current of the ad654 will cause less than one v be to be dropped. as the v/f oscillates, additional switched current is drawn through r l when pin 1 goes low. the peak level of this additional cur- rent causes q1 to saturate, and thus regenerates the ad654s output square wave at the collector. the supply voltage to the ad654 then consists of a dc level, less the resistive line drop, plus a one v be p-p square wave at the output frequency of the ad654. this ripple is reduced by the diode/capacitor combination. to set up the receiver circuit for a given voltage, the r s and r l resistances are selected as shown in table i. cmos logic stages can be driven directly from the collector of q1, and a single ttl load can be driven from the junction of r s and r6. table i. +v s r s ( v )r l ( v ) 10 v 270 1.8k 15 v 680 2.7k table ii. (+v s ) r1 ( v ) r2 ( v ) r3 ( v ) r4 ( v ) r5 ( v ) k 10 v C C C 100k 127k f = 10 hz/k 15 v C C C 100k 127k c 10 v 6.49k 4.02k 1k 95.3k 22.6k f = 10 hz/ c 15 v 12.7k 4.02k 1k 78.7k 36.5k f 10 v 6.49k 4.42k 1k 154k 22.6k f = 5.55 hz/ f 15 v 12.7k 4.42k 1k 105k 36.5k at the v/f end, the ad592c temperature transducer is inter- faced with the ad654 in such a manner that the ad654 output frequency is proportional to temperature. the output frequency can be sealed and offset from k to c or f using the resistor values shown in table ii. since temperature is the parameter of interest, an npo ceramic capacitor is used as the timing capaci- tor for low v/f tc. when scaling per k, resistors r1Cr3 and the ad589 voltage reference are not used. the ad592 produces a 1 m a/k current output which drives pin 3 of the ad654. with the timing capacitor of 0.01 m f this produces an output frequency scaled to 10 hz/k. when scaling per c and f, the ad589 and resistors r1Cr3 offset the drive current at pin 3 by 273.2 m a for scaling per c and 255.42 m a for scaling per f. this will result in fre- quencies sealed at 10 hz/ c and 5.55 hz/ f, respectively. optoisolator coupling a popular method of isolated signal coupling is via optoelec- tronic isolators, or optocouplers. in this type of device, the signal is coupled from an input led to an output photo-transistor, with light as the connecting medium. this technique allows dc to be transmitted, is extremely useful in overcoming ground loop problems between equipment, and is applicable over a wide range of speeds and power. figure 9 shows a general purpose isolated v/f circuit using a low cost 4n37 optoisolator. a +5 v power supply is assumed for both the isolated (+5 v isolated) and local (+5 v local) supplies. the input led of the isolator is driven from the collector out- put of the ad654, with a 9 ma current level established by r1 for high speed, as well as for a 100% current transfer ratio. 5v (isolated) r1 390v 4n37 opto-isolator 5v (local) grn led osc/ driver r t 1kv v in (0v to 1v) c t 1000pf ad654 r3 270v 74ls14 q1 2n3904 r2 120v v/f output fs = 100khz ttl isolated local figure 9. optoisolator interface osc/ driver ad654 v s (10v to 15v) c t 0.01mf f = i t (10v) c t r t 1mf 1n4148 r4 r5 r1 r2 r3 + C ad589 ad592 140v r s r6 220v q1 2n3906 cmos output ttl output (1 load) 1ma/kv figure 8. two-wire temperature-to-frequency converter c
ad654 C8C rev. at the receiver side, the output transistor is operated in the photo-transistor mode; that is with the base lead (pin 6) open. this allows the highest possible output current. for reasonable speed in this mode, it is imperative that the load impedance be as low as possible. this is provided by the single transistor stage current-to-voltage converter, which has a dynamic load imped- ance of less than 10 ohms and interfaces with ttl at the output. using a stand-alone frequency counter/led display driver for voltmeter applications figure 10 shows the ad654 used with a stand-alone frequency counter/led display driver. with c t = 1000 pf and r t = 1 k w the ad654 produces an fs frequency of 100 khz when v in = +1 v. this signal is fed into the icm7226a, a universal counter system that drives common anode leds. with the function pin tied to d1 through a 10 k w resistor the icm7226a counts the frequency of the signal at a in . this count period is selected by the user and can be 10 ms, 100 ms, 1s, or 10 seconds, as shown on pin 21. the longer the period selected, the more resolution the count will have. the icm7226a then displays the frequency on the leds, driving them directly as shown. refreshing of the leds is handled automatically by the icm7226. the entire circuit op- erates on a single +5 v supply and gives a meter with 3, 4, or 5 digit resolution. 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8 7 6 5 1 2 3 4 v in (0v to 1v) 5v 5v 1kv 1000pf 500v 825v 1kv ad654 di pin 30 10kv 30kv 5v 5v 10mhz crystal 22mv 39pf 39pf 5v 5v 10kv 5v d1 (10ms) d2 (100ms) d3 (1s) d4 (10s) 4 8 8 d.p. g e d c b a f led overflow indicator d8 d7 d6 d5 d4 d3 d2 d1 ain hold nc osl jn osl out nc d1 d2 d3 d4 d5 v+ d6 d7 d8 range icm7226a function dp e g a gnd d b c f + C n c = n o co nne c t figure 10. ad654 with stand-alone frequency counter/ led display driver longer count periods not only result in the count having more resolution, they also serve as an integration of noisy analog signals. for example, a normal-mode 60 hz sine wave riding on the input of the ad654 will result in the output frequency increasing on the positive half of the sine wave and decreasing on the negative half of the sine wave. this effect is cancelled by selecting a count period equal to an integral number of noise signal periods. a 100 ms count period is effective because it not only has an inte- gral number of 60 hz cycles (6), it also has an integral number of 50 hz cycles (5). this is also true of the 1 second and 10 sec- ond count period. ad654-based analog-to-digital conversion using a single chip microcomputer the ad654 can serve as an analog-to-digital converter when used with a single component microcomputer that has an inter- val timer/event counter such as the 8048. figure 11 shows the ad654, with a full-scale input voltage of +1 v and a full-scale output frequency of 100 khz, connected to the timer/counter input pin t1 of the 8048. such a system can also operate on a single +5 v supply. the 8748 counter is negative edge triggered; after the strt cnt instruction is executed subsequent high to low transitions on t1 increment the counter. the maximum rate at which the counter may be incremented is once per three instruction cycles; using a 6 mhz crystal, this corresponds to once every 7.5 m s, or a maximum frequency of 133 khz. because the counter overflows every 256 counts (8 bits), the timer interrupt is enabled. each overflow then causes a jump to a subroutine where a register is incremented. after the stop tcnt instruction is executed, the number of overflows that have occurred will be the number in this register. the number in this register multiplied by 256 plus the number in the counter will be the total number of negative edges counted during the count period. the count period is handled sim ply by decrementing a register the number of times necessary to correspond to the desired count time. after the register has been decremented the required number of times the stop tcnt instruction is executed. the total number of negative edges counted during the count period is proportional to the input voltage. for example, if a 1 v full-scale input voltage produces a 100 khz signal and the count period is 100 ms, then the total count will be 10,000. scaling from this maximum is then used to determine the input voltage, i.e., a count of 5000 corresponds to an input voltage of 0.5 v. as with the icm7226, longer count times result in counts hav- ing more resolution; and they result in the integration of noisy analog signals. c
ad654 rev. C9C 8 7 6 5 1 2 3 4 ad654 1kv v in (0v to 1v) 1000pf 5v 10kv 825v 1% 500v a d + C 6mhz 20pf 20pf 1mf xtal1 xtal2 reset ea ss int t0 t1 p10 p17 p20 p27 db0 db7 port 1 port 2 bus port v cc v dd v ss 5v gnd ale psen prog wr rd 8048 nc nc nc nc = no connect figure 11. ad654 vfc as an adc frequency doubling since the ad654s output is a square-wave rather than a pulse train, information about the input signal is carried on both halves of the output waveform. the circuit in figure 12 converts the output into a pulse train, effectively doubling the ou tput frequency, while preserving the better low frequency linearity of the ad654. this circuit also accommodates an input voltage that is greater than the ad654 supply voltage. resistors r1Cr3 are used to scale the 0 v to +10 v input voltage down to 0 v to +1 v as seen at pin 4 of the ad654. recall that v in must be less than v supply C4 v, or in this case less than 1 v. the timing resistor and capacitor are selected such that this 0 v to +1 v signal seen at pin 4 results in a 0 khz to 200 khz output frequency. the use of r4, c1 and the xor gate doubles this 200 khz output frequency to 400 khz. the ad654 output transistor is basically used as a switch, switching capacitor c1 between a charging mode and a discharging mode of operation. the voltages seen at the input of the 74ls86 are shown in the waveform dia- gram. due to the difference in the charge and discharge time constants, the output pulse widths of the 74ls86 are not equal. the output pulse is wider when the capacitor is charging due to its longer rise time than fall time. the pulses should therefore be counted on their rising, rather than falling, edges. ad654 r t 1kv c t 500pf r pu 2.87kv r3 1kv r2 2kv r1 8.06kv c1 1000pf r4 1kv 5v a b c 74ls86 v in (0v to 10v) v/f output fs = 400mhz off on v 0 v 0 5 0 transistor a b c waveform diagram osc/ driver figure 12. frequency doubler c
ad654 C10C rev. 8 7 6 5 1 2 3 4 ad654 68kv 1kv v in (0v to 1v) c t 100pf +5v 0.1mf 0.1mf r t = 1kv + C a j270 j270 q1 q2 minimum distance +15v v1 68kv v2 10mf 10mf + 5.9kv 1% (3 2) r7 8.2v minimum distance 0.1mf 10mf d C5v v3 a3-a a3-b 18v 470pf a3-c a3-d v4 a3 = 74ls86 a2 lm360 d 10mf 0.1mf +15v figure 13. 2 mhz, frequency doubling v/f operation at higher output frequencies operation of the ad654 via the conventional output (pins 1 and 2) is speed limited to approximately 500 khz for reasons of ttl logic compatibility. although the output stage may become speed lim ited, the multivibrator core itself is able to oscillate to 1 mhz or more. the designer may take advantage of this feature in order to operate the device at frequen cies in excess of 500 khz. figure 13 illustrates this with a circuit offering 2 mhz full scale. in this circuit the ad654 is operated at a full scale (fs) of 1 ma, with a c t of 100 pf. this achieves a basic device fs frequency of 1 mhz across c t . the p channel jfets, q1 and q2, buffer the differential timing capacitor waveforms to a low impedance level where the push -pull signal is then ac coupled to the high speed comparator a2. hysteresis is used, via r7, for nonambiguous switching and to eliminate the oscillations which w ould other- wise occur at low frequencies. the net result of this is a very high speed circuit which does not compromise the ad654 dynamic range. this is a result of the fet buffers typically having only a few pa of bias current. the high end dynamic range is limited, however, by parasitic package and layout capacitances in shunt with c t , as well as those from each node to ac ground. minimizing the lead length between a2C6/a2C7 and q1/q2 in pc layout will help. a ground plane will also help stability. f igure 14 shows the waveforms v1Cv4 found at the respective points shown in figure 13. the output of the comparator is a complementary square wave at 1 mhz fs. unlike pulse train output v/f converters, each half-cycle of the ad654 output conveys information about the input. thus it is possible to count edges, rather than full cycles of the output, and double the effective output frequency. the xor gate following a2 acts as an edge detector producing a short pulse for each input state transition. this effectively doubles the v/f fs frequency to 2 mhz. the final result is a 1 v full-scale input v/f with a 2 mhz full-scale output capability; typical nonlinearity is 0.5%. 100 90 10 0% 500ns 2v 5v 2v 5v 2v 0 2v 0 5v 0 5v 0 v1 v2 v3 v4 figure 14. waveforms of 2 mhz frequency doubler c
ad654 rev. c | page 11 outline dimensions figure 15. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) figure 16. 8-lead standard small outline package [soic_n] (narrow body) (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off i nch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10
ad654 rev. c | page 12 ordering guide model 1 temperature range package description package option ad654jn C40c to +85c 8-lead pdip n-8 ad654jnz C40c to +85c 8-lead pdip n-8 ad654jnz/+ C40c to +85c 8-lead pdip n-8 ad654jr C40c to +85c 8-lead soic_n r-8 ad654jr-reel C40c to +85c 8-lead soic_n r-8 AD654JR-REEL7 C40c to +85c 8-lead soic_n r-8 ad654jrz C40c to +85c 8-lead soic_n r-8 ad654jrz-reel C40c to +85c 8-lead soic_n r-8 ad654jrz-reel7 C40c to +85c 8-lead soic_n r-8 1 z = rohs compliant part. revision history 7/13rev. b to rev. c added esd caution and stresses paragraph ................................ 3 updated outline dimensions ....................................................... 11 changes to ordering guide .......................................................... 11 12/99rev. a to rev. b ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11523-0-7/13(c)

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